1. Field of the Invention
The present invention relates to scan chain stitching, and more particularly, to a method of stitching scan flipflops together to form a scan chain with a reduced wire length.
2. Description of the Related Art
Many modern day CMOS chips contain extremely complex logic functions. As a result, it is very difficult to test these chips because they often contain many thousands of flipflops that can assume many millions of logic states. Furthermore, in order to efficiently test a chip, the logic states of the chip must be easily controllable and observable. In other words, all of the flipflop outputs on a chip must be easily controllable, and these same outputs must also be easily observable. This controllability/observability, in turn, allows a complex state-dependent test problem to be reduced to a much simpler combinatorial test problem.
Flipflops are well-known logic elements that receive a data signal and a clock signal, and then retain and output the logic state of the data signal in response to an edge of the clock signal. Flipflops can respond to either the rising edge, or the falling edge, of the clock signal. Furthermore, a well-known type of flipflop is a rising-edge-triggered CMOS D flip-flop.
FIG. 1 shows an example of a prior-art circuit schematic for a rising-edge-triggered CMOS D flipflop 100. Referring to FIG. 1, flipflop 100 contains a master latch 110, a slave latch 112, and a clock inverter U1. Furthermore, except for the transistor sizes, the circuit topologies of master latch 110 and slave latch 112 are identical. This latch topology consists of two transmission gates and two inverters.
Referring to FIG. 1, when the clock input signal CLK is low, master latch transmission gate X1 will be in its turned-on state, and master latch transmission gate X2 will be in its turned-off state. Furthermore, when the clock input signal CLK is low, slave latch transmission gate X4 will be in its turned-on state, and slave latch transmission gate X3 will be in its turned-off state. Thus, when the clock input signal CLK is low, the flipflop data input DIN will be connected to the D1 input of master latch 110, and the D1Z output of master latch 110 will be disconnected from the D2Z input of slave latch 112.
In addition, when the clock input signal CLK is high, master latch transmission gate X1 will be in its turned-off state, and master latch transmission gate X2 will be in its turned-on state. Furthermore, when the clock input signal CLK is high, slave latch transmission gate X4 will be in its turned-off state, and slave latch transmission gate X3 will be in its turned-on state. Thus, when the clock input signal CLK is high, the flipflop data input DIN will be disconnected from the D1 input of master latch 110, and the master latch D1Z output will be connected to the D2Z input of slave latch 112.
As a result of the aforementioned transmission gate states, when the clock input signal CLK goes from low to high, the flipflop Q output can change state, indicating that flipflop 100 is a rising-edge-triggered flip-flop.
A serious shortcoming of flipflop 100 in FIG. 1 is that it cannot be easily tested. In other words, the flipflop output cannot be easily controlled (forced high or low) because the flipflop input DIN is connected to internal logic gates. As a consequence of this, flipflop 100 cannot be directly driven by on-chip test logic.
As well established in the prior art, a CMOS scan flipflop includes circuitry that receives additional input signals, allowing the flipflop output to be easily controlled and observed. Furthermore, a well-known type of scan flipflop is a scan-enabled rising-edge-triggered CMOS D flip-flop.
FIG. 2 shows an example of the circuit schematic for a prior-art scan-enabled rising-edge-triggered CMOS D flipflop 200. Flipflop 200 is similar to flipflop 100 and, as a result, utilizes the same reference numerals to designate the structures that are common to both flipflops. Referring to FIG. 2, flipflop 200 differs from flipflop 100 in that flipflop 200 includes a scan multiplexer (scan mux) 210.
As shown in FIG. 2, scan mux 210 consists of two transmission gates X5 and X6, and an inverter U6. In addition, scan mux 210 also has three inputs: a data input D, a scan enable input SE, and a scan data input SD. Furthermore, scan mux 210 also has a single output that drives the DIN input of flipflop master latch 110.
During normal chip operation, when the chip is not operating in scan test mode, the scan enable input SE in FIG. 2 will be low. Thus, when the scan enable input SE is low, transmission gate X6 will be turned off and transmission gate X5 will be turned on, allowing the data input D to drive the DIN input of flipflop master latch 110. The data input D, in turn, is driven by an internal on-chip logic gate.
When the chip is operating in scan test mode, the scan enable input SE in FIG. 2 will be high. Thus, when SE is high, transmission gate X6 will be turned on and transmission gate X5 will be turned off, allowing the scan data input SD to drive the DIN input of flipflop master latch 110. In other words, when the chip is operating in scan test mode, the output of flip-flop 200 can be directly controlled (forced high or low) by simply driving the scan data input SD high or low.
FIGS. 3A-3B show representations of prior-art flipflops. FIG. 3A shows a circuit symbol that represents a prior-art CMOS D flipflop 310, and FIG. 3B shows a circuit symbol that represents a prior-art scan-enabled CMOS D flipflop 312. Referring to FIGS. 3A and 3B, flipflops 310 and 312 both contain an input pin D, an input pin CLK, an output pin Q, and an inverted output pin QZ. Furthermore, scan flipflop 312 also contains two additional scan input pins, SD and SE. As described above, scan input pins SD and SE are utilized to add scan test capability to flipflop 310.
In order to control and observe the large number of scan-enabled CMOS D flipflops on a chip, the scan flipflops must be serially connected together, to form one or more scan chains. This can be accomplished as shown in FIG. 4, which shows an example of a prior-art scan chain 400.
Referring to FIG. 4, scan chain 400 includes a number of scan-enabled CMOS D flipflops 410. Thus, as shown in FIG. 4, the SD inputs of all scan-enabled flipflops 410 are controlled by simply connecting the flipflops together to form a scan chain, which is simply a serial shift register.
Referring to FIG. 4, the Q output of a given flipflop 410 is connected to the scan data input SD of the next flipflop 410 in the serial scan chain. In addition, as shown in FIG. 4, all of the SE pins in a given flipflop chain must be connected together, and all of the CLK inputs in a given flip-flop chain must also be connected together.
Furthermore, in order for a chip to function correctly in its normal operating (non-scan) mode, the Q outputs of the flipflops 410 must drive internal on-chip logic gates. Thus, as shown in FIG. 4, the arrows attached to the Q outputs of each flipflop 410 indicate that the Q outputs also drive one or more internal on-chip logic gates. (For simplicity, these logic gates are not shown in FIG. 4).
Referring to FIG. 4, the scan data input SD of the first flipflop 410 in scan chain 400 must be driven (directly or indirectly) from a primary chip input 412 (i.e., a chip input pin). This allows the state of each flipflop 410 to be controlled by simply shifting in the desired input data for each flip-flop 410. This input data is often referred to as a ‘scan input vector’.
Furthermore, the Q output from the last flipflop 410 in scan chain 400 must also be connected (directly or indirectly) to a primary chip output 414 (i.e., a chip output pin). This allows the output of each flipflop 410 in scan chain 400 to be observed by simply shifting out the state of each flipflop in the scan chain. This output data is often referred to as a ‘scan output vector’.
In order to test the internal logic gates within a chip, including all of the internal scan flipflops, input vectors must be shifted in, and the resulting output vectors must be shifted out. The output vectors are then compared with known good output vectors. If the two vectors match, the chip is said to be ‘good’. If the two vectors do not match, the chip is said to be ‘bad’. The input/output vector shifting, and the output vector comparison, are executed by a chip tester.
Before an input vector can be shifted into the chip, the scan enable inputs SE of flipflops 410 must be driven high, indicating that the chip is operating in scan test mode. As shown in FIG. 2, when the scan enable input SE is high, the DIN input data for master latch 110 comes from the scan data input SD of flipflop 200, not from the normal (non-scan) data input D.
Again referring to FIG. 4, after the scan enable input SE has been driven high, the flipflop clock signal CLK must then be pulsed until all bits of the scan input vector have been clocked into scan chain 400. As shown in FIG. 4, the bits are clocked in via the SD to Q path inside of each scan flipflop 410.
After the last bit of the scan input vector has been clocked into scan chain 400, the clock signal CLK is driven low. Furthermore, the scan enable input SE is also driven low, temporarily placing the chip in normal (non-scan) operating mode. At this point, the chip is ready to respond to the input test vector that has been serially shifted into the chip. The actual test begins when the tester issues a single clock pulse, which is often referred to as the ‘launch clock’. The launch clock causes the previously loaded input vector to determine the next state (output vector) of all flipflops 410 in scan chain 400.
Thus, after the clock signal CLK has been driven high and then low, the scan enable input SE is then driven high, forcing the chip to re-enter scan test mode, and re-enabling the SD-to-Q scan path inside of each flipflop 410. Furthermore, after the scan enable input SE is driven high, the clock signal CLK must be pulsed until all bits of the output vector have been shifted out of the chip. While the bits of the output vector are being shifted out of the chip, the bits of a new input vector are being shifted into the chip.
The above shift-in/shift-out process continues until an output vector that has been shifted out fails to match its corresponding good output vector (which is stored inside the tester). In this case, the chip test fails, and the chip is bad. Otherwise, if all of the shifted out vectors match their corresponding good output vectors (which are stored inside the tester), the chip has passed all of its test vectors, and the chip is good.
The process of serially connecting a group of scan flipflops together to form a scan chain is referred to as ‘scan stitching’. In other words, the scan stitching procedure consists of connecting the Q output of each flip-flop in a scan chain to the SD input of the next flipflop in the scan chain.
In a typical chip design flow, after logic synthesis has been completed, the flipflops are then stitched (connected) together into one or more scan chains, according to their position in the logic hierarchy. However, as described in greater detail below, this scan stitching is sub-optimal.
FIG. 5 shows a simplified example of a prior-art standard cell placement region 500. Referring to FIG. 5, standard cell placement region 500 contains eleven scan flipflops 510 that have been physically placed by a router. (For simplicity, the standard cell logic gates are not shown in FIG. 5).
Referring to FIG. 5, the scan flipflops 510 have been placed into standard cell rows, which have a uniform height. Furthermore, the standard cell rows can be touching each other, or they can be non-uniformly spaced apart.
FIG. 6 shows a simplified example of a prior-art standard cell placement region 600. Standard cell placement region 600 is similar to standard cell placement region 500 and, as a result, utilizes the same reference numerals to designate the structures which are common to both placement regions. As shown in FIG. 6, placement region 600 differs from placement region 500 in that the scan flipflops 510 in placement region 600 have been stitched together to form a scan chain 610.
In the FIG. 6 example, scan chain 610, which is created from the standard cell logic hierarchy before a router has determined the physical placement of the scan flipflops, is:

As shown in FIG. 6, the scan chain wires must necessarily snake back and forth horizontally and vertically, in the plane of the figure, in order to connect the scan flipflops together, as specified by the above scan chain. As a result of this wire routing, the scan chain wires can become long and congested. Furthermore, for simplicity, FIG. 6 does not show the common net that connects all of the scan enable inputs SE together. As described above, this common SE net must be routed (connected) to all of the scan flipflops, causing even more wire congestion than that shown in FIG. 6.
The scan stitching shown in FIG. 6 is highly undesirable for a number of reasons. Firstly, it forces the scan chain wires to make unnecessary (and often substantial) traverses in the horizontal and vertical directions. Furthermore, these unnecessary wire traverses are bad because they can substantially increase the lengths and congestion of the scan chain wires, unnecessarily increasing the capacitance on the scan flip-flop outputs. Moreover, because the wire capacitance on the scan flip-flop outputs is increased, the chip power dissipation will also be increased (in both scan mode and normal operating mode). In addition, the capacitance increase on the scan flipflop outputs can also decrease the chip operating speed.
Furthermore, the unnecessary scan wire traverses also force the router to make unnecessary metal layer changes, when routing a given scan chain. Moreover, these unnecessary metal layer changes often generate pieces of scan chain wire on several different metal layers. As a consequence of this, these pieces of scan chain wire can easily block the routing of non-scan nets, in those regions where the pieces of scan chain wire exist. In other words, the wire congestion in these regions will be increased, which can easily cause the chip size to increase.
Thus, there is a need for a routing method that, when connecting the Q-to-SD scan chain nets, and the common SE net, avoids unnecessary wire crossovers, unnecessary wire layer to wire layer changes, and unnecessary blocking of nets on several of the metal layers (i.e. ‘wrong way’ routing).
In summary, although the prior-art scan chain routing methodology functions adequately from a netlist standpoint, there is need for a method of specifying scan chain stitching that reduces the lengths of the scan chain wires, thereby reducing chip wiring congestion, chip size, flipflop load capacitance, flipflop propagation delay and flipflop power dissipation.